1. Field of the Invention
The present invention relates to a calibration method applied to the inspection of a pattern formed on a processing target substrate, an inspection method using this method, and a semiconductor device manufacturing method.
2. Description of the Related Art
In recent years, a demand for micropatterning semiconductor integrated circuits is increasing. To meet this demand, a more complicated device pattern is formed on a processing target substrate such as a wafer. It is therefore becoming difficult to determine OK (good)/NG (bad) of the pattern formed on the wafer only by observing it. Under the circumstances, the Die-to-Database inspection is becoming mainstream. In the Die-to-Database inspection, a pattern edge is extracted from a pattern image formed on a wafer, and the extracted pattern edge is compared with a target design to inspect the wafer pattern.
In view of this, threshold calibration is very important in extracting a pattern edge from an image. If the calibration is inappropriate, accurate pattern edge extraction may fail to result in an oversight of a defective pattern.
Jpn. Pat. Appln. KOKAI Publication No. 9-312318 discloses a pattern defect inspection apparatus which compares a detected wafer pattern image with a prestored reference pattern image and detects the difference as a wafer pattern defect.